1. Field of the Invention
The present invention relates to a level conversion circuit, and more particularly, to a level conversion circuit converting a first signal having one level at a reference potential and the other level at a first potential higher than the reference potential into a second signal having one level at the reference potential and the other level at a second potential higher than the first potential, to output the converted signal to an output node.
2. Description of the Background Art
Conventionally, a semiconductor integrated circuit device is provided with a level conversion circuit converting a signal VI having an amplitude voltage of a first power-supply voltage VDD into a signal VO having an amplitude voltage of a second power-supply voltage VDDH higher than first power-supply voltage VDD. In recent years, however, power-supply voltages VDD and VDDH have been lowered in order to reduce power consumption in a semiconductor integrated circuit device, which has caused a problem that the current drivability of an MOS transistor is deteriorated as first power-supply voltage VDD is lowered, reducing the operating speed of the level conversion circuit.
One method for increasing the operating speed of the level conversion circuit is to directly connect the gate and the backgate of the MOS transistor to lower a threshold voltage of the MOS transistor according to a change in level of an input signal (see Japanese Patent Laying-Open No. 2001-36388 for example).
According to this method, however, the gate and the backgate of the MOS transistor are driven by the input signal, resulting in an increase in load capacitance of the input signal, and thus a satisfactorily high operating speed cannot be achieved.
A primary object of the present invention is, therefore, to provide a level conversion circuit with a high operating speed.
According to one aspect of the present invention, a level conversion circuit converts a first signal having one level at a reference potential and the other level at a first potential higher than the reference potential into a second signal having one level at the reference potential and the other level at a second potential higher than the first potential, to output the converted signal to an output node. The level conversion circuit includes a load circuit connected between a line of the second potential and the output node; a first N-type transistor having a drain connected to the output node, a source connected to a line of the reference potential, and a gate receiving the first signal; and a bias potential generation circuit having at least one transistor rendered conductive/non-conductive in response to the first signal and generating a bias potential higher than the reference potential and at most the first potential, to apply the bias potential to a backgate of the first N-type transistor, in response to the first signal being set at the first potential. Thus, the threshold voltage of the first N-type transistor can be lowered in response to the first signal being at the first potential, increasing the operating speed.
According to another aspect of the present invention, a level conversion circuit includes a load circuit connected between a line of the second potential and the output node; an N-type transistor having a drain connected to the output node, a source connected to a line of the reference potential and a gate receiving the first signal; and a switching circuit receiving the reference potential and a bias potential that is higher than the reference potential and equal to or lower than a built-in potential of a PN junction between a backgate and a source of the N-type transistor, applying the bias potential to the backgate of the N-type transistor in response to the first signal being set at the first potential, and applying the reference potential to the backgate of the N-type transistor in response to the first signal being set at the reference potential. Thus, the threshold voltage of the N-type transistor can be lowered in response to the first signal being at the first potential, increasing the operating speed.
According to a further aspect of the present invention, a level conversion circuit includes a load circuit connected between a line of the second potential and the output node; and an N-type transistor having a drain connected to the output node, a source connected to a line of the reference potential, a gate receiving the first signal, and a backgate receiving a bias potential equal to or lower than a built-in potential of a PN junction between the backgate and the source. Thus, the threshold voltage of the N-type transistor can be lowered, increasing the operating speed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.